The present invention relates to an ion implantation method for use in the manufacture of semiconductor devices and, more particularly, to an improvement in an ion implantation method using a finely focused ion beam or a micro ion beam.
Ion implantation is a very important technique and is widely used in the manufacture of semiconductor devices. For example, in silicon metal oxide semiconductor large scale integration (to be referred to as Si-MOS-LSI), ion implantation is used for controlling the threshold voltage VTH; for formation of well regions, isolation regions, source and drain regions and the like; and for prevention of the punch-through phenomenon.
In conventional ion implantation techniques, ions are uniformly implanted into a silicon wafer as will be described hereinafter. FIGS. 1A to 1I are sectional views showing a conventional Si-MOS-LSI during various manufacturing steps using conventional ion implantation techniques. Referring to FIG. 1A first, a silicon wafer 1 is annealed in an oxygen atmosphere at 1,000.degree. C. for 20 minutes to form a silicon oxide (SiO.sub.2) film 2 of 500 .ANG. thickness. Next, referring to FIG. 1B, a silicon nitride film 3 is deposited on the silicon oxide film 2 to a thickness of about 4,000 .ANG.. After coating a resist on the silicon nitride (Si.sub.3 N.sub.4) film 3, it is patterned by general lithography to form resist patterns 4. Then, as shown in FIG. 1C, the silicon nitride film 3 is etched using the resist patterns 4 as a mask. Ion implantation of boron (B.sup.+) is performed at an acceleration voltage of 100 keV to form a p.sup.+ -type layer 5 for element isolation. Referring to FIG. 1D, after removing the resist patterns 4, field oxide films 6 of 1 .mu.m thickness are formed in an oxygen atmosphere at 1,000.degree. C. and the silicon nitride film 3 is removed thereafter. As shown in FIG. 1E, after removing the silicon oxide film 2, a gate oxide film 7 of about 300 .ANG. thickness is formed. Boron ions (B.sup.+) are uniformly implanted at an acceleration voltage of 70 keV for the purpose of controlling the threshold voltage VTH. Referring to FIG. 1F, after depositing a polysilicon film of about 3,000 .ANG. thickness over the entire surface of the structure, it is subjected to lithography and etching to form polysilicon gates 8. Subsequently, as shown in FIG. 1G, the gate oxide film 7 is etched to leave only those portions below the polysilicon gates 8. In this state, arsenic ions (As.sup.+) are implanted at an acceleration voltage of 100 keV to form source regions 9a and drain regions 9b. Referring to FIG. 1H, after depositing an insulating oxide film (SiO.sub.2) 10 of 5000 .ANG. thickness over the entire surface of the structure, a phosphate glass film 11 is deposited on the insulating oxide film 10 to a thickness of 7,000 .ANG.. The phosphate glass film 11 is heated in a nitrogen atmosphere at about 1,000.degree. C. to smoothen its surface. Contact holes are then formed by lithography and etching. After depositing an aluminum film, it is patterned to form aluminum wiring patterns 12. An Si-MOS-LSI as shown in FIG. 1I is finally manufactured.
Ion implantation adopted in the manufacture of the Si-MOS-LSI described above is uniform ion implantation in each case. MOS transistors manufactured by such a method have variations in the threshold voltage VTH according to the gate lengths and widths thereof. FIG. 2 is a graph showing the threshold voltage VTH as a function of gate length. FIG. 3 is a graph showing the threshold voltage VTH as a function of gate width. As may be seen from these graphs, with decreases in either the gate length or width of the transistors, or with micronization of the transistors, control of the threshold voltage VTH becomes difficult due to the short channel effect and the narrow channel effect. Furthermore, the problem of the punch-through phenomenon becomes more pronounced with micronization of the transistors.